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general description the max32620/max32621 is a 32-bit risc arm ? cortex ? -m4f (m4 plus floating point unit) microcon - troller. it is ideally suited for the emerging category of medical and fitness applications. the architecture com - bines high-efficiency, signal-processing functionality with low cost, and ease of use. the device features 4 powerful & flexible power modes. built-in dynamic clock gating and firmware controlled power gating minimize power con - sumption for any application. multiple spi, uart, and i 2 c serial interfaces, as well as a 1-wire ? master and usb, allow for interconnection to a wide variety of external sen - sors. a four-input, 10-bit adc with selectable references is provided. the max32621 is a secure version of the max32620, incorporating a trust protection unit (tpu) with encryption and advanced security features. applications sport watches fitness monitors wearable medical patches portable medical devices sensor hub beneits and features high-efficiency microcontroller for rechargeable devices ? internal oscillator operates up to 96mhz ? floating point unit ? memory protection unit ? 2mb flash memory ? 256kb sram ? 8kb instruction cache ? 1.2v 5% core supply voltage ? 1.8v 5% i/o and analog supply voltage ? optional 3.3v 5% usb supply voltage tiny 81-ball wlp minimizes board space (3.9mm x 3.9 mm wlp, 0.4 mm pitch) power management maximizes uptime for battery applications ? 95a/mhz active executing from flash ? 600na low power (lp0) mode with rtc enabled ? 2.5a ultra-low power data retention mode (lp1) with fast 5s (typ) wakeup to 96mhz ? peripheral management unit (pmu) reduces power consumption in measurement mode (lp2) optimal peripheral mix provides platform scalability ? three spi masters, four uarts, three i 2 c mas- ters, and one 1-wire master ? 49 general-purpose i/o pins ? spi execute in place engine for memory expan- sion with minimal footprint ? full-speed usb 2.0 with internal transceiver ? sixteen pulse train engines ? four-input, 10-bit sigma-delta adc operating at 7.8 ks/s trust protection unit (tpu) secures valuable ip and data (max32621 only) ? robust hardware internal security ? high-speed modular arithmetic accelerator (maa) supports fast ecdsa ? aes hardware engine ? hardware prng entropy generator ? secure boot loader ordering information , and additional features appear at end of data sheet. arm is a registered trademark and registered service mark and cortex is a registered trademark of arm limited. 1-wire is a registered trademark of maxim integrated products, inc. 19-7679; rev 0; 6/15 max32620/max32621 high-performance, ultra-low power cortex-m4f microcontroller for rechargeable devices downloaded from: http:///
bus matrix C ahb, apb, ibus, dbus arm cortex tm -m4f 96mhz nvic jtag swd (serial wire debug) por, brownout monitor, supply voltage monitors voltage regulation and power control clock generation 96mhz int osc/ system clock usb 2.0 full-speed controller 2048kb flash 256kb sram 8kb cache peripheral management unit 2x windowed watchdog timer rtc and wakeup timer shared pad functions timers/pwm capture/compare usb spi spi bridge spi xip i 2 c uart external interrupts aes 32-bit fifos gpio with interrupts srstn tck/swclk tms/swdio tdo tdi rstn v dda v dd12 v dd18 v rtc v ss v ssa 32kout 32kin dp dm v ddb trust protection unit (tpu) maa secure nv key prng max32621 only memory 6x 32-bit timers 16x pulse train engine 3x spi master 1x spi btle bridge 1x spi xip 16-bit fifos 3x i 2 c master 1x i 2 c slave maximum of 3 ports 32-bit fifos 4x uart 1-wire master up to 49 gpio/ special function ain0 ain1 ain2 ain3 5 5 max32620max32621 v ddb v dd18 v dd12 v rtc 10-bit sigma-delta adc v ref ext ref 1.2v 4 2 unique id crc 16/32 max32620/max32621 high-performance, ultra-low power cortex-m4f microcontroller for rechargeable devices www.maximintegrated.com maxim integrated 2 max32620/max32621 block diagram downloaded from: http:///
(all voltages with respect to v ss , unless otherwise noted.) v dd18 ................................................................ -0.3v to +1.89v v dd12 ................................................................. -0.3v to +1.26v v dda with respect to v ss\a .................................. -0.3v to +1.89v v rtc ..................................................................... -0.3v to +3.6v v ddb .................................................................... -0.3v to +3.6v v ref ..................................................................... -0.3v to +3.6v 32kin, 32kout .................................................... -0.3v to +3.6v rstn, srstn, gpio .......................................... -0.3v to +3.6v ain[1:0]................................................................. -0.3v to +5.5v ain[3:2]................................................................. -0.3v to +3.6v total current into v dd18 (sink) ......................................... 100ma total current into v ss ....................................................... 100ma output current (sink) by any i/o pin .................................. 25ma output current (source) by any i/o pin ............................. -25ma continuous power dissipation (t a = +70c) tqfp (multilayer board) (derate 45.5mw/c above +70c) ......................... 3636.4mw operating temperature range ........................... -20c to +85c storage temperature range ............................ -65c to +150c soldering temperature (reflow) ....................................... +260c (note 1) tqfp junction-to-ambient thermal resistance ( ja ) .......... 22c/w junction-to-case thermal resistance ( jc ) ................. 2c/w wlp junction-to-ambient thermal resistance ( ja ) .......... 36c/w (limits are tested at t a = +20c and t a = +85c. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. specifications marked gbd are guaranteed by design and not production tested.) parameter symbol conditions min typ max units supply voltage v dd18 1.71 1.8 1.89 v v dd12 1.14 1.2 1.26 v dda 1.71 1.8 1.89 v rtc 1.71 1.8 1.89 v ddb 3.04 3.3 3.60 power-fail reset voltage v rst monitors v dd18 1.62 1.70 v power on reset voltage v por monitors v dd18 1.5 v ram data retention voltage v drv 0.94 v v dd12 dynamic current, lp3 mode i dd12_dlp3 executing code from cache memory, 95 a/mhz v dd12 current, lp3 mode i dd12_lp3 system clock stopped 490 a v dd18 current, lp3 mode i dd18_lp3 executing code from cache memory, all inputs are tied to v ss or v dd18 , outputs do not source/sink any current 360 a max32620/max32621 high-performance, ultra-low power cortex-m4f microcontroller for rechargeable devices www.maximintegrated.com maxim integrated 3 note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . absolute maximum ratings this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. package thermal characteristicselectrical characteristics downloaded from: http:///
(limits are tested at t a = +20c and t a = +85c. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. specifications marked gbd are guaranteed by design and not production tested.) parameter symbol conditions min typ max units v rtc current, lp3 mode i rtc_lp3 rtc disabled 105 na rtc enabled 805 na v dd12 dynamic current, lp2 mode i dd12_dlp2 arm in sleep mode, pmu with two channels active 27 a/mhz v dd12 current, lp2 mode i dd12_lp2 arm in sleep mode, system clock stopped 490 a v dd18 current, lp2 mode i dd18_lp2 arm in sleep mode, pmu with two channels active, all inputs are tied to v ss or v dd18 , outputs do not source/sink any current 360 a v rtc current, lp2 mode i rtc_lp2 rtc disabled 105 na rtc enabled 805 na v dd12 current, lp1 mode i dd12_lp1 standby state with full data retention 0 a v dd18 current, lp1 mode i dd18_lp1 standby state with full data retention 2.5 a v rtc current, lp1 mode i rtc_lp1 rtc disabled 105 na rtc enabled 505 na v dd12 current, lp0 mode i dd12_lp0 0 na v dd18 current, lp0 mode i dd18_lp0 120 na v rtc current, lp0 mode i rtc_lp0 rtc disabled 105 na rtc enabled 505 na lp2 mode resume time t lp2_on 0 s lp1 mode resume time tlp1_on 5 s lp0 mode resume time t lp0_on 15 s clocksinternal relaxation oscillator frequency f intclk factory default 94.08 96.0 97.92 mhz firmware trimmed, required for usb compliance 95.76 96.0 96.24 mhz system clock frequency f ck 0.371 97.92 mhz system clock period t ck 1/f ck max32620/max32621 high-performance, ultra-low power cortex-m4f microcontroller for rechargeable devices www.maximintegrated.com maxim integrated 4 electrical characteristics (continued) downloaded from: http:///
(limits are tested at t a = +20c and t a = +85c. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. specifications marked gbd are guaranteed by design and not production tested.) parameter symbol conditions min typ max units rtc input frequency f 32kin 32khz watch crystal (6pf) 32.768 khz rtc power up time t rtc_ on 250 ms general purpose i/o input low voltage for rstn , srstn , and all port pins v il 0.3 x v dd18 v input high voltage for rstn , srstn , and all port pins v ih 0.7 x v dd18 v input hysteresis (schmitt) v ihys 100 mv output low voltage for all port pins v ol i ol = 4ma (normal drive) 0.2 0.4 v i ol = 24ma (high drive) 0.2 0.4 v combined i ol , all gpio i ol_total 48 ma output high voltage for all port pins v oh i oh = -2ma (normal drive) v dd18 - 0.4 v i oh = -8ma (high drive) v dd18 - 0.4 v combined i oh , all gpio i oh_total 48 ma input/output pin capacitance for all port pins c io 5 pf input leakage current low i il v dd18 = 1.89v v in = 0v, internal pullup disabled -100 +100 na input leakage current high i ih v dd18 = 1.89v, v in = 1.89v, internal pulldown disabled -100 +100 na i off v dd18 = 0v, v in < 1.89v -1 +1 a i ih3v v dd18 = 1.71v, v in = 3.60v -1 +1 a input pullup resistor rstn , srstn , tms, tck, tdi r pu 25 k? input pullup/pulldown all gpio r pu_gpio normal resistance mode 25 k? highest resistance mode 1 m? flash memory page size 8 kb flash erase time t m_erase mass erase 30 ms t p_erase page erase 30 ms flash programming time per word t prog 60 s flash endurance 10 kcycles data retention t ret t a = +85c 10 years max32620/max32621 high-performance, ultra-low power cortex-m4f microcontroller for rechargeable devices www.maximintegrated.com maxim integrated 5 electrical characteristics (continued) downloaded from: http:///
(limits are tested at t a = +20c and t a = +85c. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. specifications marked gbd are guaranteed by design and not production tested.) (limits are tested at t a = +20c and t a = +85c. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. specifications marked gbd are guaranteed by design and not production tested.) parameter symbol conditions min typ max units single-ended input high voltage dp, dm v ihd 2.0 v single-ended input low voltage dp, dm v ild 0.8 v output low voltage dp, dm v old r l = 1.5k? from dp to 3.6v 0.3 v output high voltage dp, dm v ohd r l = 15k? from dp and dm to v ss 2.8 v differential input sensitivity dp, dm v di dp to dm 0.2 v common-mode voltage range v cm includes v di range 0.8 2.5 v single-ended receiver threshold v se 0.8 2.0 v single-ended receiver hysteresis v seh 200 mv differential output signal cross-point voltage v crs c l = 50pf, gbd 1.3 2.0 v dp, dm off-state input impedance r lz 300 k? driver output impedance r drv steady-state drive 28 44 ? dp pullup resistor r pu idle 0.9 1.575 k? receiving 1.425 3.090 usb timing dp, dm rise time (transmit) t r c l = 50pf, gbd 4 20 ns dp, dm fall time (transmit) t f c l = 50pf, gbd 4 20 ns rise/fall time matching (transmit) t r , t f c l = 50pf, gbd 90 110 % parameter symbol conditions min typ max units resolution 10 bits adc clock rate f aclk 0.1 8 mhz adc clock period t aclk 1/ f aclk s input voltage range v ain ain[3:0], adc_chsel = 0C3, buf_bypass = 1 v ss v dda v ain[1:0], adc_chsel = 4C5, buf_bypass = 1 v ss 5.5v ain[3:0], adc_chsel = 0C3, buf_bypass = 0 50mv v dda - 50mv ain[1:0], adc_chsel = 4-5, buf_bypass = 0 50mv 5.5v adc electrical characteristics max32620/max32621 high-performance, ultra-low power cortex-m4f microcontroller for rechargeable devices www.maximintegrated.com maxim integrated 6 usb electrical characteristics downloaded from: http:///
(limits are tested at t a = +20c and t a = +85c. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. specifications marked gbd are guaranteed by design and not production tested.) parameter symbol conditions min typ max units input impedance r ain ain[1:0], adc_hsel = 4C5, adc active 45 k? input dynamic current, switched capacitance i ain adc active, adc buffer bypassed 4.5 a adc active, adc buffer enabled 50 na analog input capacitance c ain fixed capacitance to ground 1 pf dynamically switched capacitance 250 nf integral nonlinearity inl 2 lsb differential nonlinearity dnl 1 lsb offset error v os 1 lsb gain error ge 2 lsb adc active current i adc adc active, reference buffer enabled, input buffer disabled 240 a input buffer active current i inbuf 53 a adc setup time t adc_su any power-up of: adc clock, adc bias, reference buffer, or input buffer to cpuadcstart 10 s any power-up of: adc clock or adc bias to cpuadcstart 48 t aclk adc output latency t adc 1025 t aclk adc sample rate f adc 7.80 ksps adc input leakage i adc_leak ain0 or ain1, adc inactive or channel not selected 0.12 4 na ain2 or ain3, adc inactive or channel not selected 0.02 1.0 na ain0/ain1 resistor divider error adc_chsel = 4 or 5, not including adc offset/gain error 2 lsb full-scale voltage v fs adc code = 0x3ff 1.200 v signal to noise ratio snr 58.5 db signal to noise and distortion sinad 58.5 db total harmonic distortion thd -68.5 db spurious free dynamic range sfdr 74 db bandgap temperature coeficient v tempco box method 30 ppm/c reference input capacitance c ref_in dynamically switched capacitance, adc_ xref=1, adc active 250 ff external reference voltage v ref_ext adc_xref = 1 1.17 1.23 1.29 v reference dynamic current i ref_ext adc_xref=1, adc active 4.1 a max32620/max32621 high-performance, ultra-low power cortex-m4f microcontroller for rechargeable devices www.maximintegrated.com maxim integrated 7 adc electrical characteristics (continued) downloaded from: http:///
100 tqfp- ep 1 n.c. 2 v dd18 3 v ss 4 p1.6 5 p1.5 6 p1.4 7 v ss 8 v dd12 9 p1.3 10 p1.2 11 p1.1 12 p1.0 13 n.c. 14 p0.7 15 p0.6 16 p0.5 17 p0.4 18 p0.3 19 p0.2 20 p0.1 21 p0.0 22 rstn 23 srstn 24 p6.0 25 n.c. 75 n.c. 74 p4.0 73 p4.1 72 p4.2 71 p4.3 70 p4.4 69 p4.5 68 p4.6 67 p4.7 66 n.c. 65 dm 64 dp 63 v dd18 62 v ss 61 v ddb 60 v ss 59 v rtc 58 v ss 57 n.c. 56 32kout 55 32kin 54 n.c. 53 n.c. 52 n.c. 51 n.c. 50 n.c. 49 p5.0 48 p5.1 47 p5.2 46 v dd18 45 p5.3 44 p5.4 43 n.c. 42 v ss 41 ain3 40 tdi 39 ain2 38 tdo 37 ain1 35 ain0 34 v ref 32 n.c. 31 tck 29 v dda 28 p5.6 27 p5.7 30 p5.5 33 v ssa 36 tms n.c. 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 91 92 94 95 97 98 99 96 93 90 100 n.c.n.c. n.c. p3.7p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 n.c. p2.7p2.6 v dd18 p2.5p2.3 p2.2 p2.0 n.c. p1.7 p2.1 p2.4 v ss n.c. + top view max32620max32621 ep* *ep = exposed pad max32620/max32621 high-performance, ultra-low power cortex-m4f microcontroller for rechargeable devices www.maximintegrated.com maxim integrated 8 pin coniguration downloaded from: http:///
1 2 3 4 5 6 7 8 9 a + top view (bump side down) b cd e f g h j max32620max32621 100 wlp v ssa v ref ain0 ain1 ain2 ain3 v dd18 n.c. rstn v dda tck tms tdo tdi v ss 32kin p0.0 p6.0 p5.7 p5.5 p5.4 p5.2 v rtc 32kout p0.5 p0.3 p0.2 p5.6 p5.3 p5.0 v ddb v ss p0.7 p0.6 p1.1 p1.5 p3.1 p5.1 dp v dd18 p1.3 p1.2 p1.4 p3.0 p3.5 p3.7 dm p4.7 p1.6 p1.7 p2.4 p2.6 p3.4 p4.4 p4.6 p4.5 p2.1 p2.2 p2.5 p2.7 p3.2 p4.1 p4.3 p4.2 p2.0 p2.3 v dd18 v ss p3.3 p3.6 p4.0 n.c. n.c. srstn p0.1 p0.4 p1.0 v dd12 v ss v dd18 n.c. max32620/max32621 high-performance, ultra-low power cortex-m4f microcontroller for rechargeable devices www.maximintegrated.com maxim integrated 9 pin coniguration (continued) downloaded from: http:///
pin name function tqfp wlp power 61 d8 v ddb usb transceiver supply voltage. this pin must be bypassed to v ss with a 1.0f capacitor as close to this pin as possible. 8 f1 v dd12 1.2v supply voltage. this pin must be bypassed to v ss with a 100nf capacitor as close to this pin as possible. 59 c8 v rtc rtc supply voltage. this pin must be bypassed to v ss with a 1.0f capacitor as close to this pin as possible. 29 b3 v dda analog supply voltage. this pin must be bypassed to v ssa with a 1.0f capacitor as close to this pin as possible 2, 46, 63, 91 a8, e9, h1, j4 v dd18 1.8v supply voltage. this pin must be bypassed to v ss with a 1.0f capacitor as close to this pin as possible. 34 a3 v ref adc reference. this pin should be left unconnected if an external reference is not used. 3, 7, 42, 58, 60, 62, 90 b8, d9, g1, j5 v ss digital ground. 33 a2 v ssa analog ground. this pin must be connected to v ss. ep exposed pad (tqfp only). this pad must be connected to v ss . refer to application note 3273: exposed pads: a brief introduction for additional information. clocks 55 b9 32kin 32khz crystal oscillator input/output. connect a 6pf 32khz crystal between 32kin and 32kout for rtc operation. optionally, an external clock source can be driven on 32kin if the 32kout pin is left unconnected. a 32khz crystal or external clock source is required for proper usb operation. 56 c9 32kout usb 64 e8 dp usb d+ signal. this bidirectional pin carries the positive differential data or single- ended data. this pin is weakly pulled high internally when the usb is disabled. 65 f8 dm usb d- signal. this bidirectional pin carries the negative differential data or single- ended data. this pin is weakly pulled high internally when the usb is disabled. jtag 31 b4 tck jtag clock or serial wire debug clock. this pin has an internal 25k? pullup to v dd18 . 36 b5 tms jtag test mode select or serial wire debug i/o. this pin has an internal 25k? pullup to v dd18 . 38 b6 tdo jtag test data output 40 b7 tdi jtag test data input. this pin has an internal 25k? pullup to v dd18 . max32620/max32621 high-performance, ultra-low power cortex-m4f microcontroller for rechargeable devices www.maximintegrated.com maxim integrated 10 pin description downloaded from: http:///
pin name function tqfp wlp reset 22 b2 rstn hardware reset, active-low input. the device remains in reset while this pin is in its active state. when the pin transitions to its inactive state, the device performs a por reset (resetting all logic on all supplies except for real-time clock circuitry) and begins execution. this pin has an internal 25k? pullup to the v rtc supply. this pin should be left unconnected if the system design does not provide a reset signal to the device. 23 b1 srstn software reset, active-low input/output. the device remains in software reset while this pin is in its active state. when the pin transitions to its inactive state, the device performs a reset to the arm core, digital registers and peripherals (resetting most of the core logic on the v dd12 supply). this reset does not affect the por only registers, rtc logic, arm debug engine or jtag debugger allowing for a soft reset without having to reconiguring all registers. after the device senses srstn as a logic 0, the pin automatically reconigures as an output sourcing a logic 0. the device continues to output for 6 system clock cycles and then repeats the input sensing/output driving until srstn is sensed inactive. this pin is internally connected with an internal 25k? pullup to the v rtc supply. this pin should be left unconnected if the system design does not provide a reset signal to the device. general-purpose i/o and special functions 21 c2 p0.0 general-purpose i/o, port 0. most port pins have multiple special functions. see table 1 for details. 20 c1 p0.1 19 d4 p0.2 18 d3 p0.3 17 d1 p0.4 16 d2 p0.5 15 e3 p0.6 14 e2 p0.7 12 e1 p1.0 general-purpose i/o, port 1. most port pins have multiple special functions. see table 1 for details. 11 e4 p1.1 10 f3 p1.2 9 f2 p1.3 6 f4 p1.4 5 e5 p1.5 4 g2 p1.6 99 g3 p1.7 max32620/max32621 high-performance, ultra-low power cortex-m4f microcontroller for rechargeable devices www.maximintegrated.com maxim integrated 11 pin description (continued) downloaded from: http:///
pin name function tqfp wlp 97 j2 p2.0 general-purpose i/o, port 2. most port pins have multiple special functions. see table 1 for details. 96 h2 p2.1 95 h3 p2.2 94 j3 p2.3 93 g4 p2.4 92 h4 p2.5 89 g5 p2.6 88 h5 p2.7 86 f5 p3.0 general-purpose i/o, port 3. most port pins have multiple special functions. see table 1 for details. 85 e6 p3.1 84 h6 p3.2 83 j6 p3.3 82 g6 p3.4 81 f6 p3.5 80 j7 p3.6 79 f7 p3.7 74 j8 p4.0 general-purpose i/o, port 4. most port pins have multiple special functions. see table 1 for details. 73 h7 p4.1 72 h9 p4.2 71 h8 p4.3 70 g7 p4.4 69 g9 p4.5 68 g8 p4.6 67 f9 p4.7 49 d7 p5.0 general-purpose i/o, port 5. most port pins have multiple special functions. see table 1 for details. 48 e7 p5.1 47 c7 p5.2 45 d6 p5.3 44 c6 p5.4 30 c5 p5.5 28 d5 p5.6 27 c4 p5.7 24 c3 p6.0 general-purpose i/o, port 6.0. most port pins have multiple special functions. see table 1 for details. max32620/max32621 high-performance, ultra-low power cortex-m4f microcontroller for rechargeable devices www.maximintegrated.com maxim integrated 12 pin description (continued) downloaded from: http:///
table 1. max326320/max32621 gpio special function cross reference gpio special functions p0.0 uart0a_rx uart0b_tx pt_pt0 timer_tmr0 gpio_int(p0) p0.1 uart0a_tx uart0b_rx pt_pt1 timer_tmr1 gpio_int(p0) p0.2 uart0a_cts uart0b_rts pt_pt2 timer_tmr2 gpio_int(p0) p0.3 uart0a_rts uart0b_cts pt_pt3 timer_tmr3 gpio_int(p0) p0.4 spim0_sck pt_pt4 timer_tmr4 gpio_int(p0) p0.5 spim0_mosi/ sdio0 pt_pt5 timer_tmr5 gpio_int(p0) p0.6 spim0_miso/ sdio1 pt_pt6 timer_tmr0 gpio_int(p0) p0.7 spim0_ss0 pt_pt7 timer_tmr1 gpio_int(p0) p1.0 spim1_sck spix_sck pt_pt8 timer_tmr2 gpio_int(p1) p1.1 spim1_mosi/ sdio0 spix_sdio0 pt_pt9 timer_tmr3 gpio_int(p1) p1.2 spim1_miso/ sdio1 spix_sdio1 pt_pt10 timer_tmr4 gpio_int(p1) p1.3 spim1_ss0 spix_ss pt_pt11 timer_tmr5 gpio_int(p1) p1.4 spim1_sdio2 spix_sdio2 pt_pt12 timer_tmr0 gpio_int(p1) p1.5 spim1_sdio3 spix_sdio3 pt_pt13 timer_tmr1 gpio_int(p1) p1.6 i2cm0/sa_sda pt_pt14 timer_tmr2 gpio_int(p1) p1.7 i2cm0/sa_scl pt_pt15 timer_tmr3 gpio_int(p1) p2.0 uart1a_rx uart1b_tx pt_pt0 timer_tmr4 gpio_int(p2) p2.1 uart1a_tx uart1b_rx pt_pt1 timer_tmr5 gpio_int(p2) pin name function tqfp wlp analog input pins 35 a4 ain0 adc input 0. 5v-tolerant input. 37 a5 ain1 adc input 1. 5v-tolerant input. 39 a6 ain2 adc input 2 41 a7 ain3 adc input 3 no connects 1, 13, 25, 26, 32, 43, 50C54, 57, 66, 75C78, 87, 98, 100 a1, a9, j1, j9 n.c. no connection max32620/max32621 high-performance, ultra-low power cortex-m4f microcontroller for rechargeable devices www.maximintegrated.com maxim integrated 13 pin description (continued) downloaded from: http:///
table 1. max326320/max32621 gpio special function cross reference (continued) gpio special functions p2.2 uart1a_cts uart1b_rts pt_pt2 timer_tmr0 gpio_int(p2) p2.3 uart1a_rts uart1b_cts pt_pt3 timer_tmr1 gpio_int(p2) p2.4 spim2a_sck pt_pt4 timer_tmr2 gpio_int(p2) p2.5 spim2a_mosi/ sdio0 pt_pt5 timer_tmr3 gpio_int(p2) p2.6 spim2a_miso/ sdio1 pt_pt6 timer_tmr4 gpio_int(p2) p2.7 spim2a_ss0 pt_pt7 timer_tmr5 gpio_int(p2) p3.0 uart2a_rx uart2b_tx pt_pt8 timer_tmr0 gpio_int(p3) p3.1 uart2a_tx uart2b_rx pt_pt9 timer_tmr1 gpio_int(p3) p3.2 uart2a_cts uart2b_rts pt_pt10 timer_tmr2 gpio_int(p3) p3.3 uart2a_rts uart2b_cts pt_pt11 timer_tmr3 gpio_int(p3) p3.4 i2cm1/sb_sda spim2a_ss1 pt_pt12 timer_tmr4 gpio_int(p3) p3.5 i2cm1/sb_scl spim2a_ss2 pt_pt13 timer_tmr5 gpio_int(p3) p3.6 spim1_ss1 spix_ss1 pt_pt14 timer_tmr0 gpio_int(p3) p3.7 spim1_ss2 spix_ss2 pt_pt15 timer_tmr1 gpio_int(p3) p4.0 owm_i/o spim2a_sr0 pt_pt0 timer_tmr2 gpio_int(p4) p4.1 owm_pupen spim2a_sr1 pt_pt1 timer_tmr3 gpio_int(p4) p4.2 spim0_sdio2 pt_pt2 timer_tmr4 gpio_int(p4) p4.3 spim0_sdio3 pt_pt3 timer_tmr5 gpio_int(p4) p4.4 spim0_ss1 pt_pt4 timer_tmr0 gpio_int(p4) p4.5 spim0_ss2 pt_pt5 timer_tmr1 gpio_int(p4) p4.6 spim0_ss3 pt_pt6 timer_tmr2 gpio_int(p4) p4.7 spim0_ss4 pt_pt7 timer_tmr3 gpio_int(p4) p5.0 spib_sck spim2b_sck pt_pt8 timer_tmr4 gpio_int(p5) p5.1 spib_sdio0 spim2b_ mosi/sdio0 pt_pt9 timer_tmr5 gpio_int(p5) p5.2 spib_sdio1 spim2b_ miso/sdio1 pt_pt10 timer_tmr0 gpio_int(p5) p5.3 spib_ssn0 spim2b_ss0 uart3a_rx uart3b_tx pt_pt11 timer_tmr1 gpio_int(p5) p5.4 spib_sdio2 spim2b_ sdio2 uart3a_tx uart3b_rx pt_pt12 timer_tmr2 gpio_int(p5) p5.5 spib_sdio3 spim2b_ sdio3 uart3a_cts uart3b_rts pt_pt13 timer_tmr3 gpio_int(p5) p5.6 spib_srn spim2b_sr uart3a_rts uart3b_cts pt_pt14 timer_tmr4 gpio_int(p5) p5.7 i2cm2/sc_sda spim2b_ss1 pt_pt15 timer_tmr5 gpio_int(p5) p6.0 i2cm2/sc_scl spim2b_ss2 pt_pt0 timer_tmr0 gpio_int(p5) max32620/max32621 high-performance, ultra-low power cortex-m4f microcontroller for rechargeable devices www.maximintegrated.com maxim integrated 14 downloaded from: http:///
max32620/max32621 detailed description the max32620/max3261 is a low-power, mixed signal microcontroller based on the arm cortex-m4f 32-bit core with a maximum operating frequency of 96mhz. the max32621 is a secure version, incorporating a trust pro - tection unit (tpu) with encryption and advanced security features. application code executes from an onboard 2mb pro - gram flash memory, with 256kb sram available for gen - eral application use. an 8kb instruction cache improves execution throughput, and a transparent code scrambling scheme protects customer intellectual property residing in the program flash memory. additionally, a spi execute in place (xip) external memory interface allows applica - tion code and data (up to 16mb) to be accessed from an external spi memory device. a 10-bit sigma-delta adc is provided with a multiplexer front end for four external input channels (two of which are 5.5v tolerant) and six internal channels. dedicated divided supply input channels allows direct monitoring of onboard power supplies v dd12 , v dd18 , v ddb and v rtc by the adc. built-in limit monitors allow converted input samples to be compared against user-configurable high and low limits, with an option to trigger an interrupt and wake the cpu from a low power mode if attention is required. a wide variety of communications and interface peripher - als are provided, including a usb 2.0-compliant slave interface, three master spi interfaces, four uart inter - faces with multidrop support, three master i 2 c interfaces, and a slave i 2 c interface. arm cortex-m4f architecture the arm cortex-m4f processor is ideal for the emerging category of wearable medical and wellness applications. the architecture combines high-efficiency signal process - ing functionality with low power, low cost, and ease of use. floating point unit (fpu) memory protection unit full debug support level ? debug access port (dap) ? breakpoints ? dwt ? flash patch ? halting debug debug access port : jtag or serial wire nvic support ? 52 interrupts to be grouped by irmware into 8 levels of priority cortex-m4f dsp supports single instruction multiple data (simd) path dsp extensions, providing: ? 4 parallel 8 bit add/sub ? 2 parallel 16 bit add/sub ? 2 parallel macs ? 32 or 64 bit accumulate ? signed, unsigned, data with or without saturation analog to digital converter (adc) the 10-bit sigma-delta adc provides 4 external inputs and can also be configured to measure all internal power supplies. it operates at a maximum of 7.8ksps. ain0 and ain1 are 5.5v tolerant, making them suitable for monitor - ing batteries. an optional feature allows samples captured by the adc to be automatically compared against user-programmable high and low limits. up to four channel limit pairs can be configured in this way. the comparison allows the adc to trigger an interrupt (and potentially wake the cpu from a low power sleep mode) when a captured sample goes outside the preprogrammed limit range. since this comparison is performed directly by the sample limit monitors, it can be performed even while the main cpu is suspended in a low-power mode. the adc reference is selectable: internal bandgap external reference pulse train engine sixteen independent pulse train generators provide either a square wave or a repeating pattern from 2 bits to 32 bits in length. the frequency of each enabled pulse train generator is also set separately, based on a divide down (divide by 2, divide by 4, divide by 8, etc.) of the input pulse train module clock. any single pulse train generator or any desired group of pulse train generators can be restarted at the beginning of their patterns and synchronized with one another ensur - ing simultaneous startup. additionally, each pulse train can operate in a single shot mode. max32620/max32621 high-performance, ultra-low power cortex-m4f microcontroller for rechargeable devices www.maximintegrated.com maxim integrated 15 downloaded from: http:///
clocking scheme the high-frequency internal relaxation oscillator operates at a nominal frequency of 96mhz. it is the primary clock source for the digital logic and peripherals. an external 32.766khz timebase is required when using the rtc or usb features of the device. the time base can be generated by attaching a 32khz crystal. an exter - nal clock source can also be applied to the 32kin pin. the external clock source must meet the electrical/timing requirements in the ec table. the 32khz output can be directed out to pin p1.7 for observation and use. interrupt sources the arm nested vector interrupt controller (nvic) pro - vides high speed, deterministic interrupt response, inter - rupt masking, and multiple interrupt sources. each periph - eral is connected to the nvic and can have multiple interrupt flags to indicate the specific source of the inter - rupt within the peripheral. 52 interrupts can be grouped by irmware into 8 levels of priority (including internal and external interrupts). figure 1. clock diagram real-time clock power sequencer usb phy nano-ring oscillator ~8khz firmware frequency calibration divide by 2 core clock scaler arm ? cortex ? -m4 core internal 96mhz oscillator rtc oscillator internal 44mhz cryptographic oscillator tpu adc clock scaler adc xtal driver or external clock 32kin 32kout 32khz crystal gpio 1.7 32.768khz output clock 32khz always-on domain 48mhz 380khzC 96mhz 8mhz 44mhz trust protection unit (max32621 only) max32620/max32621 high-performance, ultra-low power cortex-m4f microcontroller for rechargeable devices www.maximintegrated.com maxim integrated 16 downloaded from: http:///
real-time clock a real-time clock (rtc) keeps the time of day in absolute seconds. the 32-bit seconds register can count up to approximately 136 years and be translated to calendar format by application software. a time-of-day alarm and independent subsecond alarm can cause an interrupt or wake the device from stop mode. the minimum wake-up interval is 244s. crc module the crc hardware module provides fast calculations and data integrity checks by application software. the crc module supports both the crc-16-ccitt and crc-32 (x 32 +x 26 +x 23 +x 2 2 +x 16 +x 12 +x 11 +x 10 +x 8 +x 7 +x 5 +x 4 +x 2 +x 1 +1)polynomials. watchdog timers two independent watchdog timers (wdt) with window support are provided. the wdt has multiple clock source options to ensure system security. it uses a 32-bit timer with prescaler to generate the watchdog reset. when enabled, the wdt must be reset prior to timeout or within a window of time if window mode is enabled. failure to reset the wdt during the programmed timing window results in a watchdog timeout. wtd resets can cause firmware or power-on resets. the wdt1 or wdt2 flags are set on reset if a watchdog expiration caused the sys - tem reset. the clock source options for the wdt include: scaled-system clock rtc clock nano-ring management clock programmable timers six 32-bit timers provide timing, capture/compare, or generation of pulse-width modulated (pwm) signals. each timer can be split into 2 16-bit timers, enabling 12 standard 16-bit timers. 32-bit timer features: 32-bit up/down auto-reload programmable 16-bit prescaler pwm output generation capture, compare, and capture/compare capability gpios can be assigned as external timer inputs, clock gating or capture, limited to an input frequency of 1/4 of the peripheral clock frequency timer output pin configurable as 2x 16-bit general purpose timers timer interrupt figure 2. timer block diagram, 32-bit mode timer control register 32 bit timer (with prescaler) 32 bit compare register 32 bit pwm/compare compare compare interrupt pwm and timer output control time interrupt register apb bus apb clock timerinterrupt timer output timer input max32620 max32621 timer block max32620/max32621 high-performance, ultra-low power cortex-m4f microcontroller for rechargeable devices www.maximintegrated.com maxim integrated 17 downloaded from: http:///
serial peripherals usb controller the integrated usb controller is compliant with the full- speed (12mb/s) usb 2.0 specification. the integrated usb physical interface (phy) reduces board space and system cost. an integrated voltage regulator allows for smart switching between the main supply and v ddb when connected to a usb host controller. the usb controller supports dma for the endpoint buf - fers. a total of 7 endpoint buffers are supported with con - figurable selection of in or out in addition to endpoint 0. an external 32khz crystal or clock source is required for usb operation, even if the rtc function is not used. although the usb timing is derived from the internal 96mhz oscillator, the default accuracy is not sufficient for usb operation. firmware trimming of the 96mhz oscilla - tor, using the 32khz timebase as a reference, is neces - sary to comply with usb timing requirements.i 2 c master and slave ports the i 2 c interface is a bidirectional, 2-wire serial bus that provides a medium-speed communications network. it can operate as a one-to-one, one-to-many or many- to-many communications medium. three i 2 c master engines and one i 2 c-selectable slave engine interface to a wide variety of i 2 c-compatible peripherals. these engines support both standard mode and fast mode i 2 c standards. the slave engine shares the same i/o port as the master engines and is selectable through the i/o configuration settings. it provides the following features: master or slave mode operation information transferal over a serial data circuit (sda) and serial clock circuit (scl) supports standard (7-bit) addressing support for clock stretching to allow slower slave devices to operate on higher speed busses multiple transfer rates: standard mode: 100kbpsfast mode: 400kbps on-chip filter to reject spikes on the data circuit receiver fifo depth of 16 bytes transmitter fifo depth of 16 bytes serial peripheral interface master interface the spi master-mode-only interface operates indepen - dently in a single or multiple slave system and is fully accessible to the user application. the spi ports provide a highly configurable, flexible and efficient interface to communicate with a wide variety of spi slave devices. the three spi master ports (spi0, spi1, spi2) support the following features: supports all four spi modes (0,1,2,3) for single-bit communication 3 or 4 wire mode for single-bit slave device commu- nication full-duplex operation in single-bit, 4-wire mode dual and quad i/o supported up to 5 slave select lines per port up to 2 slave ready lines programmable interface timing programmable sck frequency and duty cycle programmable sck alternate timing ss (slave select) assertion and deassertion timing with respect to leading/trailing sck edge serial peripheral interface execute in place (xip) master the spi execute in place (xip) master allows the cpu to transparently execute instructions stored in an external spi flash. instructions fetched through the spi xip mas - ter are cached just like instructions fetched from internal program memory. the spi xip master can also be used to access large amounts of external static data that would otherwise reside in internal data memory. uart all four universal asynchronous receiver-transmitter (uart) interfaces support full-duplex asynchronous com - munication with optional hardware flow control (hfc) modes to prevent data overruns. if hfc mode is enabled on a given port, the system uses two extra pins to imple - ment the industry-standard request to send (rts) and clear to send (cts) methodology. each uart is individu - ally programmable. 2-wire interface or 4-wire interface with low control 2x 32-byte send/receive fifos, one for transmit and receive full-duplex operation for asynchronous data transfers programmable interrupt for receive and transmit independent baud-rate generator programmable 9th bit parity support start/stop bit support hardware low control using rts/cts maximum baud rate 460.8kb max32620/max32621 high-performance, ultra-low power cortex-m4f microcontroller for rechargeable devices www.maximintegrated.com maxim integrated 18 downloaded from: http:///
trust protection unit (tpu) (max32621 only) the tpu enhances cryptographic data security for valu - able intellectual property (ip) and data. a high-speed, dedicated, hardware-based math accelerator (maa) per - forms mathematical computations that support strong cryptographic algorithms including: aes-128 aes-192 aes-256 1024-bit dsa 2048-bit (crt) the device provides a pseudo-random number genera - tor which can be used to create cryptographic keys for any application. a user-selectable entropy source further increases the randomness and key strength. the secure bootloader protects against unauthorized access to program memory. peripheral management unit (pmu) the pmu is a dma-based link list processing engine that performs operations and data transfers involving memory and/or peripherals in the advanced peripheral bus (apb) and advanced high-performance bus (ahb) peripheral memory space while the main cpu is in a sleep state. this allows low-overhead peripheral operations to be performed without the cpu, significantly reducing overall power consumption. using the pmu with the cpu in a sleep state provides a lower-noise environment critical for obtaining optimum adc performance. key features of the pmu engine include: six independent channels with round-robin schedul- ing allows for multiple parallel operations programmed using sram-based pmu opcodes pmu action can be initiated from interrupt conditions from peripherals without cpu integrated ahb bus master coprocessor-like state machine additional documentation engineers must have the following documents to fully use this device: this data sheet, containing pin descriptions, feature overviews, and electrical speciications the device-appropriate user guide, containing detailed information and programming guidelines for core features and peripherals errata sheets for speciic revisions noting deviations from published speciications. for information regarding these documents, visit technical support at support.maximintegrated.com/micro . development and technical support contact technical support for information about highly versatile, affordable development tools, available from maxim integrated and third-party vendors. evaluation kits software development kit compilers integrated development environments (ides) usb interface modules for programming and debugging for technical support, go to support.maximintegrated. com/micro . max32620/max32621 high-performance, ultra-low power cortex-m4f microcontroller for rechargeable devices www.maximintegrated.com maxim integrated 19 downloaded from: http:///
additional features arm ? cortex ? -m4f 32 bit risc cpu ? internal 96mhz oscillator saves board space and cost ? memory protection unit ? floating point unit ultra-low power ? 95a/mhz dynamic power executing from flash ? 600na (typ) low power mode lp0 current with rtc enabled ? 2.5a ultra-low power data retention mode lp1 with fast 5s (typ) wakeup ? dynamic clock disables unused peripherals/logic ? wake up from rtc, usb, gpio, multiple/single events peripherals ? 3x spi master engines (1/2/4-bit width) ? 1x spi master xip engine for external flash execution ? 3x i 2 c master engines (fast/standard mode) ? 1x i 2 c slave engine (shared pins with master engines) ? 4x uart with optional hardware flow control ? 1x 1-wire master ? 16x pulse train engines ? usb 2.0-compliant peripheral, full speed (12mb/s) ? 6x 32-bit timers (reconigurable as 12 x 16-bit timers) ? 32 bit real-time clock (rtc) with time of day alarm ? supports 1149.1 jtag with serial wire debug memory ? 2mb flash memory ? 8kb instruction cache ? 256kb sram supply voltage ? 1.2v 5% core supply voltage ? 1.8v 5% i/o and analog supply voltage ? optional 3.3v 5% usb supply voltage other features: ? 49 general purpose i/o (gpio) ? 2x programmable watchdog timers with indepen- dent clock sources analog components ? four-input, 10-bit sigma-delta adc operating at 7.8 ks/s ? 5.5v, 1.2v-tolerant inputs ? internal or external reference peripheral management unit (pmu) reduces power consumption in sleep mode trust protection unit for data integrity and ip protection ? aes hardware engine ? maa for ecdsa and modular arithmetic ? trust protection unit (tpu) for end-to-end security ? hardware prng entropy generator ? secure boot loader ? crc16/32 engine ? factory-programmed unique id max32620/max32621 high-performance, ultra-low power cortex-m4f microcontroller for rechargeable devices www.maximintegrated.com maxim integrated 20 downloaded from: http:///
max32620max32621 power manager i/o arm cortex tm - m4f and digital core usb phy v ddb 3.3v ldo2 l2out analog v dda 1.8v buck1 b1out v dd18 pmic ctrl interface i 2 c cfg/ctrl interface rtc v rtc 1.8v ldo1 l1out 32khz v dd12 b2out 1.2v buck2 pwrmgr usb drvp drvn bip bin ecgp ecgn int0 fclk max14690 pmic max30003 ecg afe li-ion spi external ecg connectors ble radio 24mhz rst spi bridge v dd12 max32620/max32621 high-performance, ultra-low power cortex-m4f microcontroller for rechargeable devices www.maximintegrated.com maxim integrated 21 typical application circuitelectrocardiogram (ecg) patch downloaded from: http:///
+denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. package type package code outline no. land pattern no. 81 wlp w813d3+1 21-0776 refer to application note 1891 100 tqfp-ep c100e+3 21-0116 90-0154 part flash (mb) sram (kb) trust protection unit pin-package max32620icq+ 2 256 no 100 tqfp max32620iwg+ 2 256 no 81 wlp max32620iwg+t 2 256 no 81 wlp max32621icq+ 2 256 yes 100 tqfp max32621iwg+ 2 256 yes 81 wlp max32621iwg+t 2 256 yes 81 wlp max32620/max32621 high-performance, ultra-low power cortex-m4f microcontroller for rechargeable devices www.maximintegrated.com maxim integrated 22 ordering information package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. downloaded from: http:///
revision number revision date description pages changed 0 6/15 initial release maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. max32620/max32621 high-performance, ultra-low power cortex-m4f microcontroller for rechargeable devices ? 2015 maxim integrated products, inc. 23 revision history for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

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